FPGA driver support
This patch is not a plugin implementation
Cyborg agent can call driver as follow:
from cyborg.accelerator.drivers.fpga import base
fdriver = base.FPGADriver
# There maybe more than one vendor fpga card on a host.
venders = fdriver.discover_vendors()
for v in venders:
dr = fdriver.create(v)
dr.discover()
intel = base.FPGADriver.create("intel")
intel.program("/fpga/device/path", "/local/path/image")
When call IntelFPGADriver.discover(), we can get the result as follow:
[{'assignable': False,
'devices': '0000:5e:00.0',
'function': 'pf',
'parent_devices': '',
'path': '/sys/class/fpga/intel-fpga-dev.0',
'pr_num': '1',
'product_id': '0xbcc0',
'regions': [{'assignable': True,
'devices': '0000:5e:00.1',
'function': 'vf',
'parent_devices': '0000:5e:00.0',
'path': '/sys/class/fpga/intel-fpga-dev.2',
'product_id': '0xbcc1',
'vendor_id': '0x8086'}],
'vendor_id': '0x8086'},
{'assignable': True,
'devices': '0000:be:00.0',
'function': 'pf',
'parent_devices': '',
'path': '/sys/class/fpga/intel-fpga-dev.1',
'pr_num': '0',
'product_id': '0xbcc0',
'vendor_id': '0x8086'}]
Cyborg agent can use it to form it's DB.
Co-Authored-By: Dolpher Du <Dolpher.Du@intel.com>
Change-Id: I132be5ecdb90b385b68b0cdf306d1402ef4bfc04
This commit is contained in:
Shaohe Feng
parent
b22761ab0d
commit
5b72422930
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# Copyright 2018 Intel, Inc.
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#
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# Licensed under the Apache License, Version 2.0 (the "License"); you may
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# not use this file except in compliance with the License. You may obtain
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# a copy of the License at
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#
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# http://www.apache.org/licenses/LICENSE-2.0
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#
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# Unless required by applicable law or agreed to in writing, software
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# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
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# License for the specific language governing permissions and limitations
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# under the License.
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import os
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import glob
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from oslo_log import log as logging
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__import__('pkg_resources').declare_namespace(__name__)
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__import__(".".join([__package__, 'base']))
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LOG = logging.getLogger(__name__)
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def load_fpga_vendor_driver():
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files = glob.glob(os.path.join(os.path.dirname(__file__), "*/driver*"))
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modules = set(map(lambda s: ".".join(s.rsplit(".")[0].rsplit("/", 2)[-2:]),
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files))
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for m in modules:
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try:
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__import__(".".join([__package__, m]))
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LOG.debug("Successfully loaded FPGA vendor driver: %s." % m)
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except ImportError as e:
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LOG.error("Failed to load FPGA vendor driver: %s. Details: %s"
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% (m, e))
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load_fpga_vendor_driver()
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# Copyright 2018 Intel, Inc.
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#
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# Licensed under the Apache License, Version 2.0 (the "License"); you may
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# not use this file except in compliance with the License. You may obtain
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# a copy of the License at
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#
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# http://www.apache.org/licenses/LICENSE-2.0
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#
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# Unless required by applicable law or agreed to in writing, software
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# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
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# License for the specific language governing permissions and limitations
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# under the License.
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"""
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Cyborg FPGA driver implementation.
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"""
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from cyborg.accelerator.drivers.fpga import utils
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VENDOR_MAPS = {"0x8086": "intel"}
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class FPGADriver(object):
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"""Base class for FPGA drivers.
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This is just a virtual FPGA drivers interface.
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Vedor should implement their specific drivers.
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"""
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@classmethod
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def create(cls, vendor, *args, **kwargs):
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for sclass in cls.__subclasses__():
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vendor = VENDOR_MAPS.get(vendor, vendor)
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if vendor == sclass.VENDOR:
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return sclass(*args, **kwargs)
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raise LookupError("Not find the FPGA driver for vendor %s" % vendor)
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def __init__(self, *args, **kwargs):
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pass
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def discover(self):
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raise NotImplementedError()
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def program(self, device_path, image):
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raise NotImplementedError()
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@classmethod
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def discover_vendors(cls):
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return utils.discover_vendors()
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# Copyright 2018 Intel, Inc.
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#
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# Licensed under the Apache License, Version 2.0 (the "License"); you may
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# not use this file except in compliance with the License. You may obtain
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# a copy of the License at
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#
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# http://www.apache.org/licenses/LICENSE-2.0
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#
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# Unless required by applicable law or agreed to in writing, software
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# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
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# License for the specific language governing permissions and limitations
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# under the License.
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"""
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Cyborg Intel FPGA driver implementation.
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"""
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import subprocess
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from cyborg.accelerator.drivers.fpga.base import FPGADriver
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from cyborg.accelerator.drivers.fpga.intel import sysinfo
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class IntelFPGADriver(FPGADriver):
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"""Base class for FPGA drivers.
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This is just a virtual FPGA drivers interface.
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Vedor should implement their specific drivers.
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"""
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VENDOR = "intel"
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def __init__(self, *args, **kwargs):
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pass
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def discover(self):
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return sysinfo.fpga_tree()
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def program(self, device_path, image):
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bdf = ""
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path = sysinfo.find_pf_by_vf(device_path) if sysinfo.is_vf(
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device_path) else device_path
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if sysinfo.is_bdf(device_path):
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bdf = sysinfo.get_pf_bdf(device_path)
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else:
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bdf = sysinfo.get_bdf_by_path(path)
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bdfs = sysinfo.split_bdf(bdf)
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cmd = ["sudo", "fpgaconf"]
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for i in zip(["-b", "-d", "-f"], bdfs):
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cmd.extend(i)
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cmd.append(image)
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p = subprocess.Popen(cmd, stdout=subprocess.PIPE)
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# FIXME Should log p.communicate(), p.stderr
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p.wait()
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return p.returncode
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# Copyright 2018 Intel, Inc.
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#
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# Licensed under the Apache License, Version 2.0 (the "License"); you may
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# not use this file except in compliance with the License. You may obtain
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# a copy of the License at
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#
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# http://www.apache.org/licenses/LICENSE-2.0
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#
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# Unless required by applicable law or agreed to in writing, software
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# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
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# License for the specific language governing permissions and limitations
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# under the License.
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"""
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Cyborg Intel FPGA driver implementation.
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"""
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# from cyborg.accelerator.drivers.fpga.base import FPGADriver
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import glob
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import os
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import re
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SYS_FPGA = "/sys/class/fpga"
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DEVICE = "device"
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PF = "physfn"
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VF = "virtfn*"
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BDF_PATTERN = re.compile(
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"^[a-fA-F\d]{4}:[a-fA-F\d]{2}:[a-fA-F\d]{2}\.[a-fA-F\d]$")
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DEVICE_FILE_MAP = {"vendor": "vendor_id",
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"device": "product_id",
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"sriov_numvfs": "pr_num"}
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DEVICE_FILE_HANDLER = {}
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DEVICE_EXPOSED = ["vendor", "device", "sriov_numvfs"]
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def all_fpgas():
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# glob.glob1("/sys/class/fpga", "*")
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return glob.glob(os.path.join(SYS_FPGA, "*"))
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def all_vf_fpgas():
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return [dev.rsplit("/", 2)[0] for dev in
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glob.glob(os.path.join(SYS_FPGA, "*/device/physfn"))]
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def all_pure_pf_fpgas():
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return [dev.rsplit("/", 2)[0] for dev in
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glob.glob(os.path.join(SYS_FPGA, "*/device/virtfn0"))]
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def target_symbolic_map():
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maps = {}
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for f in glob.glob(os.path.join(SYS_FPGA, "*/device")):
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maps[os.path.realpath(f)] = os.path.dirname(f)
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return maps
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def bdf_path_map():
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maps = {}
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for f in glob.glob(os.path.join(SYS_FPGA, "*/device")):
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maps[os.path.basename(os.path.realpath(f))] = os.path.dirname(f)
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return maps
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def all_vfs_in_pf_fpgas(pf_path):
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maps = target_symbolic_map()
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vfs = glob.glob(os.path.join(pf_path, "device/virtfn*"))
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return [maps[os.path.realpath(vf)] for vf in vfs]
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def all_pf_fpgas():
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return [dev.rsplit("/", 2)[0] for dev in
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glob.glob(os.path.join(SYS_FPGA, "*/device/sriov_totalvfs"))]
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def is_vf(path):
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return True if glob.glob(os.path.join(path, "device/physfn")) else False
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def find_pf_by_vf(path):
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maps = target_symbolic_map()
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p = os.path.realpath(os.path.join(path, "device/physfn"))
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return maps[p]
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def is_bdf(bdf):
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return True if BDF_PATTERN.match(bdf) else False
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def get_bdf_by_path(path):
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return os.path.basename(os.readlink(os.path.join(path, "device")))
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def split_bdf(bdf):
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return ["0x" + v for v in bdf.replace(".", ":").rsplit(":")[1:]]
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def get_pf_bdf(bdf):
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path = bdf_path_map().get(bdf)
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if path:
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path = find_pf_by_vf(path) if is_vf(path) else path
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return get_bdf_by_path(path)
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return bdf
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def fpga_device(path):
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infos = {}
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def read_line(filename):
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with open(filename) as f:
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return f.readline().strip()
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# NOTE "In 3.x, os.path.walk is removed in favor of os.walk."
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for (dirpath, dirnames, filenames) in os.walk(path):
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for filename in filenames:
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if filename in DEVICE_EXPOSED:
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key = DEVICE_FILE_MAP.get(filename) or filename
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if key in DEVICE_FILE_HANDLER and callable(
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DEVICE_FILE_HANDLER(key)):
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infos[key] = DEVICE_FILE_HANDLER(key)(
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os.path.join(dirpath, filename))
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else:
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infos[key] = read_line(os.path.join(dirpath, filename))
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return infos
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def fpga_tree():
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def gen_fpga_infos(path, vf=True):
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name = os.path.basename(path)
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dpath = os.path.realpath(os.path.join(path, DEVICE))
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bdf = os.path.basename(dpath)
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func = "vf" if vf else "pf"
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pf_bdf = os.path.basename(
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os.path.realpath(os.path.join(dpath, PF))) if vf else ""
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fpga = {"path": path, "function": func,
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"devices": bdf, "assignable": True,
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"parent_devices": pf_bdf,
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"name": name}
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d_info = fpga_device(dpath)
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fpga.update(d_info)
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return fpga
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devs = []
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pure_pfs = all_pure_pf_fpgas()
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for pf in all_pf_fpgas():
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fpga = gen_fpga_infos(pf, False)
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if pf in pure_pfs:
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fpga["assignable"] = False
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fpga["regions"] = []
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vfs = all_vfs_in_pf_fpgas(pf)
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for vf in vfs:
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vf_fpga = gen_fpga_infos(vf, True)
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fpga["regions"].append(vf_fpga)
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devs.append(fpga)
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return devs
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# Copyright 2018 Intel, Inc.
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#
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# Licensed under the Apache License, Version 2.0 (the "License"); you may
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# not use this file except in compliance with the License. You may obtain
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# a copy of the License at
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#
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# http://www.apache.org/licenses/LICENSE-2.0
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#
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# Unless required by applicable law or agreed to in writing, software
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# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
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# License for the specific language governing permissions and limitations
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# under the License.
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"""
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Utils for FPGA driver.
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"""
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import glob
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import re
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VENDORS = ["intel"] # can extend, such as ["intel", "xilinx"]
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SYS_FPGA_PATH = "/sys/class/fpga"
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VENDORS_PATTERN = re.compile("|".join(["(%s)" % v for v in VENDORS]))
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def discover_vendors():
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vendors = set()
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for p in glob.glob1(SYS_FPGA_PATH, "*"):
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m = VENDORS_PATTERN.match(p)
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if m:
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vendors.add(m.group())
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return list(vendors)
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# Copyright 2018 Intel, Inc.
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#
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# Licensed under the Apache License, Version 2.0 (the "License"); you may
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# not use this file except in compliance with the License. You may obtain
|
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# a copy of the License at
|
||||
#
|
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# http://www.apache.org/licenses/LICENSE-2.0
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#
|
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# Unless required by applicable law or agreed to in writing, software
|
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# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
|
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# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
|
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# License for the specific language governing permissions and limitations
|
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# under the License.
|
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import mock
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import os
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import subprocess
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import fixtures
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from cyborg.accelerator.drivers.fpga.base import FPGADriver
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from cyborg.accelerator.drivers.fpga.intel import sysinfo
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from cyborg.tests import base
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from cyborg.tests.unit.accelerator.drivers.fpga.intel import prepare_test_data
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class TestFPGADriver(base.TestCase):
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def setUp(self):
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super(TestFPGADriver, self).setUp()
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self.syspath = sysinfo.SYS_FPGA
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sysinfo.SYS_FPGA = "/sys/class/fpga"
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tmp_sys_dir = self.useFixture(fixtures.TempDir())
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prepare_test_data.create_fake_sysfs(tmp_sys_dir.path)
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sysinfo.SYS_FPGA = os.path.join(
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tmp_sys_dir.path, sysinfo.SYS_FPGA.split("/", 1)[-1])
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def tearDown(self):
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super(TestFPGADriver, self).tearDown()
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sysinfo.SYS_FPGA = self.syspath
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def test_create(self):
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FPGADriver.create("intel")
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self.assertRaises(LookupError, FPGADriver.create, "xilinx")
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def test_discover(self):
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d = FPGADriver()
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self.assertRaises(NotImplementedError, d.discover)
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def test_program(self):
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d = FPGADriver()
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self.assertRaises(NotImplementedError, d.program, "path", "image")
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def test_intel_discover(self):
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expect = [{'function': 'pf', 'assignable': False, 'pr_num': '1',
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'vendor_id': '0x8086', 'devices': '0000:5e:00.0',
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'regions': [{
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'function': 'vf', 'assignable': True,
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'product_id': '0xbcc1',
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'name': 'intel-fpga-dev.2',
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'parent_devices': '0000:5e:00.0',
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'path': '%s/intel-fpga-dev.2' % sysinfo.SYS_FPGA,
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'vendor_id': '0x8086',
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'devices': '0000:5e:00.1'}],
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'name': 'intel-fpga-dev.0',
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'parent_devices': '',
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'path': '%s/intel-fpga-dev.0' % sysinfo.SYS_FPGA,
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'product_id': '0xbcc0'},
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{'function': 'pf', 'assignable': True, 'pr_num': '0',
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'vendor_id': '0x8086', 'devices': '0000:be:00.0',
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'name': 'intel-fpga-dev.1',
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'parent_devices': '',
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'path': '%s/intel-fpga-dev.1' % sysinfo.SYS_FPGA,
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'product_id': '0xbcc0'}]
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expect.sort()
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intel = FPGADriver.create("intel")
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fpgas = intel.discover()
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fpgas.sort()
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self.assertEqual(2, len(fpgas))
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self.assertEqual(fpgas, expect)
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@mock.patch.object(subprocess, 'Popen', autospec=True)
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def test_intel_program(self, mock_popen):
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class p(object):
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returncode = 0
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def wait(self):
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pass
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||||
b = "0x5e"
|
||||
d = "0x00"
|
||||
f = "0x0"
|
||||
expect_cmd = ['sudo', 'fpgaconf', '-b', b,
|
||||
'-d', d, '-f', f, '/path/image']
|
||||
mock_popen.return_value = p()
|
||||
intel = FPGADriver.create("intel")
|
||||
# program VF
|
||||
intel.program("0000:5e:00.1", "/path/image")
|
||||
mock_popen.assert_called_with(expect_cmd, stdout=subprocess.PIPE)
|
||||
|
||||
# program PF
|
||||
intel.program("0000:5e:00.0", "/path/image")
|
||||
mock_popen.assert_called_with(expect_cmd, stdout=subprocess.PIPE)
|
||||
|
|
@ -0,0 +1,93 @@
|
|||
# Copyright 2018 Intel, Inc.
|
||||
#
|
||||
# Licensed under the Apache License, Version 2.0 (the "License"); you may
|
||||
# not use this file except in compliance with the License. You may obtain
|
||||
# a copy of the License at
|
||||
#
|
||||
# http://www.apache.org/licenses/LICENSE-2.0
|
||||
#
|
||||
# Unless required by applicable law or agreed to in writing, software
|
||||
# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
|
||||
# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
|
||||
# License for the specific language governing permissions and limitations
|
||||
# under the License.
|
||||
|
||||
import mock
|
||||
import os
|
||||
import subprocess
|
||||
|
||||
import fixtures
|
||||
|
||||
from cyborg.accelerator.drivers.fpga.intel import sysinfo
|
||||
from cyborg.accelerator.drivers.fpga.intel.driver import IntelFPGADriver
|
||||
from cyborg.tests import base
|
||||
from cyborg.tests.unit.accelerator.drivers.fpga.intel import prepare_test_data
|
||||
|
||||
|
||||
class TestIntelFPGADriver(base.TestCase):
|
||||
|
||||
def setUp(self):
|
||||
super(TestIntelFPGADriver, self).setUp()
|
||||
self.syspath = sysinfo.SYS_FPGA
|
||||
sysinfo.SYS_FPGA = "/sys/class/fpga"
|
||||
tmp_sys_dir = self.useFixture(fixtures.TempDir())
|
||||
prepare_test_data.create_fake_sysfs(tmp_sys_dir.path)
|
||||
sysinfo.SYS_FPGA = os.path.join(
|
||||
tmp_sys_dir.path, sysinfo.SYS_FPGA.split("/", 1)[-1])
|
||||
|
||||
def tearDown(self):
|
||||
super(TestIntelFPGADriver, self).tearDown()
|
||||
sysinfo.SYS_FPGA = self.syspath
|
||||
|
||||
def test_discover(self):
|
||||
expect = [{'function': 'pf', 'assignable': False, 'pr_num': '1',
|
||||
'vendor_id': '0x8086', 'devices': '0000:5e:00.0',
|
||||
'regions': [{
|
||||
'function': 'vf', 'assignable': True,
|
||||
'product_id': '0xbcc1',
|
||||
'name': 'intel-fpga-dev.2',
|
||||
'parent_devices': '0000:5e:00.0',
|
||||
'path': '%s/intel-fpga-dev.2' % sysinfo.SYS_FPGA,
|
||||
'vendor_id': '0x8086',
|
||||
'devices': '0000:5e:00.1'}],
|
||||
'name': 'intel-fpga-dev.0',
|
||||
'parent_devices': '',
|
||||
'path': '%s/intel-fpga-dev.0' % sysinfo.SYS_FPGA,
|
||||
'product_id': '0xbcc0'},
|
||||
{'function': 'pf', 'assignable': True, 'pr_num': '0',
|
||||
'vendor_id': '0x8086', 'devices': '0000:be:00.0',
|
||||
'parent_devices': '',
|
||||
'name': 'intel-fpga-dev.1',
|
||||
'path': '%s/intel-fpga-dev.1' % sysinfo.SYS_FPGA,
|
||||
'product_id': '0xbcc0'}]
|
||||
expect.sort()
|
||||
|
||||
intel = IntelFPGADriver()
|
||||
fpgas = intel.discover()
|
||||
fpgas.sort()
|
||||
self.assertEqual(2, len(fpgas))
|
||||
self.assertEqual(fpgas, expect)
|
||||
|
||||
@mock.patch.object(subprocess, 'Popen', autospec=True)
|
||||
def test_intel_program(self, mock_popen):
|
||||
|
||||
class p(object):
|
||||
returncode = 0
|
||||
|
||||
def wait(self):
|
||||
pass
|
||||
|
||||
b = "0x5e"
|
||||
d = "0x00"
|
||||
f = "0x0"
|
||||
expect_cmd = ['sudo', 'fpgaconf', '-b', b,
|
||||
'-d', d, '-f', f, '/path/image']
|
||||
mock_popen.return_value = p()
|
||||
intel = IntelFPGADriver()
|
||||
# program VF
|
||||
intel.program("0000:5e:00.1", "/path/image")
|
||||
mock_popen.assert_called_with(expect_cmd, stdout=subprocess.PIPE)
|
||||
|
||||
# program PF
|
||||
intel.program("0000:5e:00.0", "/path/image")
|
||||
mock_popen.assert_called_with(expect_cmd, stdout=subprocess.PIPE)
|
||||
|
|
@ -0,0 +1,296 @@
|
|||
#!/usr/bin/python
|
||||
# Copyright 2018 Intel, Inc.
|
||||
#
|
||||
# Licensed under the Apache License, Version 2.0 (the "License"); you may
|
||||
# not use this file except in compliance with the License. You may obtain
|
||||
# a copy of the License at
|
||||
#
|
||||
# http://www.apache.org/licenses/LICENSE-2.0
|
||||
#
|
||||
# Unless required by applicable law or agreed to in writing, software
|
||||
# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
|
||||
# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
|
||||
# License for the specific language governing permissions and limitations
|
||||
# under the License.
|
||||
|
||||
import argparse
|
||||
import copy
|
||||
import glob
|
||||
import os
|
||||
import shutil
|
||||
|
||||
|
||||
PF0_ADDR = "0000:5e:00.0"
|
||||
PF1_ADDR = "0000:be:00.0"
|
||||
VF0_ADDR = "0000:5e:00.1"
|
||||
FPGA_TREE = {
|
||||
"dev.0": {"bdf": PF0_ADDR,
|
||||
"regions": {"dev.2": {"bdf": VF0_ADDR}}},
|
||||
"dev.1": {"bdf": PF1_ADDR}}
|
||||
|
||||
SYS_DEVICES = "sys/devices"
|
||||
SYS_CLASS_FPGA = "sys/class/fpga"
|
||||
|
||||
DEV_PREFIX = "intel-fpga"
|
||||
|
||||
PGFA_DEVICE_COMMON_SUB_DIR = ["power"]
|
||||
|
||||
PGFA_DEVICE_COMMON_CONTENT = {
|
||||
"broken_parity_status": "0",
|
||||
"class": "0x120000",
|
||||
"config": "",
|
||||
"consistent_dma_mask_bits": "64",
|
||||
"d3cold_allowed": "1",
|
||||
"device": "0xbcc0",
|
||||
"dma_mask_bits": "64",
|
||||
"driver_override": "(null)",
|
||||
"enable": "1",
|
||||
"irq": "16",
|
||||
"local_cpulist": "0-111",
|
||||
"local_cpus": "00000000,00000000,00000000,00000000,00000000,"
|
||||
"00000000,00000000,00000000,00000000,00000000,"
|
||||
"0000ffff,ffffffff,ffffffff,ffffffff",
|
||||
"modalias": "pci:v00008086d0000BCC0sv00000000sd00000000bc12sc00i00",
|
||||
"msi_bus": "",
|
||||
"numa_node": "-1",
|
||||
"resource": [
|
||||
"0x00000000c6000000 0x00000000c607ffff 0x000000000014220c",
|
||||
"0x0000000000000000 0x0000000000000000 0x0000000000000000",
|
||||
"0x00000000c6080000 0x00000000c60fffff 0x000000000014220c",
|
||||
"0x0000000000000000 0x0000000000000000 0x0000000000000000",
|
||||
"0x0000000000000000 0x0000000000000000 0x0000000000000000",
|
||||
"0x0000000000000000 0x0000000000000000 0x0000000000000000",
|
||||
"0x0000000000000000 0x0000000000000000 0x0000000000000000",
|
||||
"0x00000000c6100000 0x00000000c617ffff 0x000000000014220c",
|
||||
"0x0000000000000000 0x0000000000000000 0x0000000000000000",
|
||||
"0x0000000000000000 0x0000000000000000 0x0000000000000000",
|
||||
"0x0000000000000000 0x0000000000000000 0x0000000000000000",
|
||||
"0x0000000000000000 0x0000000000000000 0x0000000000000000",
|
||||
"0x0000000000000000 0x0000000000000000 0x0000000000000000"],
|
||||
"resource0": "",
|
||||
"resource0_wc": "",
|
||||
"subsystem_device": "0x0000",
|
||||
"subsystem_vendor": "0x0000",
|
||||
"uevent": [
|
||||
"DRIVER=intel-fpga-pci",
|
||||
"PCI_CLASS=120000",
|
||||
"PCI_ID=8086:BCC0",
|
||||
"PCI_SUBSYS_ID=0000:0000",
|
||||
"PCI_SLOT_NAME=0000:5e:00.0",
|
||||
"MODALIAS=pci:v00008086d0000BCC0sv00000000sd00000000bc12sc00i00"],
|
||||
"vendor": "0x8086"}
|
||||
|
||||
PGFA_DEVICES_SPECIAL_COMMON_CONTENT = {
|
||||
"dev.0": {
|
||||
"resource2": "",
|
||||
"resource2_wc": "",
|
||||
"sriov_numvfs": "1",
|
||||
"sriov_totalvfs": "1",
|
||||
},
|
||||
"dev.1": {
|
||||
"resource": [
|
||||
"0x00000000fbc00000 0x00000000fbc7ffff 0x000000000014220c",
|
||||
"0x0000000000000000 0x0000000000000000 0x0000000000000000",
|
||||
"0x00000000fbc80000 0x00000000fbcfffff 0x000000000014220c",
|
||||
"0x0000000000000000 0x0000000000000000 0x0000000000000000",
|
||||
"0x0000000000000000 0x0000000000000000 0x0000000000000000",
|
||||
"0x0000000000000000 0x0000000000000000 0x0000000000000000",
|
||||
"0x0000000000000000 0x0000000000000000 0x0000000000000000",
|
||||
"0x00000000fbd00000 0x00000000fbd7ffff 0x000000000014220c",
|
||||
"0x0000000000000000 0x0000000000000000 0x0000000000000000",
|
||||
"0x0000000000000000 0x0000000000000000 0x0000000000000000",
|
||||
"0x0000000000000000 0x0000000000000000 0x0000000000000000",
|
||||
"0x0000000000000000 0x0000000000000000 0x0000000000000000",
|
||||
"0x0000000000000000 0x0000000000000000 0x0000000000000000"],
|
||||
"resource2": "",
|
||||
"resource2_wc": "",
|
||||
"sriov_numvfs": "0",
|
||||
"sriov_totalvfs": "1",
|
||||
"uevent": [
|
||||
"DRIVER=intel-fpga-pci",
|
||||
"PCI_CLASS=120000",
|
||||
"PCI_ID=8086:BCC0",
|
||||
"PCI_SUBSYS_ID=0000:0000",
|
||||
"PCI_SLOT_NAME=0000:be:00.0",
|
||||
"MODALIAS=pci:v00008086d0000BCC0sv00000000sd00000000bc12sc00i00"],
|
||||
},
|
||||
"dev.2": {
|
||||
"d3cold_allowed": "0",
|
||||
"device": "0xbcc1",
|
||||
"modalias": "pci:v00008086d0000BCC0sv00000000sd00000000bc12sc00i00",
|
||||
"irq": "0",
|
||||
"resource": [
|
||||
"0x00000000c6100000 0x00000000c617ffff 0x000000000014220c",
|
||||
"0x0000000000000000 0x0000000000000000 0x0000000000000000",
|
||||
"0x0000000000000000 0x0000000000000000 0x0000000000000000",
|
||||
"0x0000000000000000 0x0000000000000000 0x0000000000000000",
|
||||
"0x0000000000000000 0x0000000000000000 0x0000000000000000",
|
||||
"0x0000000000000000 0x0000000000000000 0x0000000000000000",
|
||||
"0x0000000000000000 0x0000000000000000 0x0000000000000000",
|
||||
"0x0000000000000000 0x0000000000000000 0x0000000000000000",
|
||||
"0x0000000000000000 0x0000000000000000 0x0000000000000000",
|
||||
"0x0000000000000000 0x0000000000000000 0x0000000000000000",
|
||||
"0x0000000000000000 0x0000000000000000 0x0000000000000000",
|
||||
"0x0000000000000000 0x0000000000000000 0x0000000000000000",
|
||||
"0x0000000000000000 0x0000000000000000 0x0000000000000000"],
|
||||
"uevent": [
|
||||
"DRIVER=intel-fpga-pci",
|
||||
"PCI_CLASS=120000",
|
||||
"PCI_ID=8086:BCC1",
|
||||
"PCI_SUBSYS_ID=0000:0000",
|
||||
"PCI_SLOT_NAME=0000:5e:00.1",
|
||||
"MODALIAS=pci:v00008086d0000BCC1sv00000000sd00000000bc12sc00i00"],
|
||||
}
|
||||
}
|
||||
|
||||
PGFA_DEVICE_COMMON_SOFT_LINK = {
|
||||
"driver": "../../../bus/pci/drivers/intel-fpga-pci",
|
||||
"iommu": "../../virtual/iommu/dmar8",
|
||||
"iommu_group": "../../../kernel/iommu_groups/75",
|
||||
"subsystem": "../../../bus/pci"
|
||||
}
|
||||
|
||||
PGFA_DEVICES_SPECIAL_SOFT_LINK = {
|
||||
"dev.0": {
|
||||
"firmware_node": "../../LNXSYSTM:00/device:00/PNP0A08:18/device:1d4",
|
||||
},
|
||||
"dev.1": {
|
||||
"firmware_node": "../../LNXSYSTM:00/device:00/PNP0A08:19/device:1d5",
|
||||
"iommu": "../../virtual/iommu/dmar4",
|
||||
"iommu_group": "../../../kernel/iommu_groups/76",
|
||||
},
|
||||
"dev.2": {
|
||||
"iommu": "../../virtual/iommu/dmar9",
|
||||
"iommu_group": "../../../kernel/iommu_groups/81",
|
||||
}
|
||||
}
|
||||
PGFA_DEVICES_SPECIAL_SOFT_LINK = {
|
||||
"dev.0": {
|
||||
"firmware_node": "../../LNXSYSTM:00/device:00/PNP0A08:18/device:1d4",
|
||||
},
|
||||
"dev.1": {
|
||||
"firmware_node": "../../LNXSYSTM:00/device:00/PNP0A08:19/device:1d5",
|
||||
"iommu": "../../virtual/iommu/dmar4",
|
||||
"iommu_group": "../../../kernel/iommu_groups/76",
|
||||
},
|
||||
"dev.2": {
|
||||
"iommu": "../../virtual/iommu/dmar9",
|
||||
"iommu_group": "../../../kernel/iommu_groups/81",
|
||||
}
|
||||
}
|
||||
|
||||
PGFA_DEVICE_PF_SOFT_LINK = {
|
||||
"virtfn": lambda k, v: (k + str(int(v.rsplit(".", 1)[-1]) - 1),
|
||||
"/".join(["..", v]))
|
||||
}
|
||||
|
||||
PGFA_DEVICE_VF_SOFT_LINK = {
|
||||
"physfn": lambda k, v: (k, "/".join(["..", v]))
|
||||
}
|
||||
|
||||
|
||||
def gen_fpga_content(path, dev):
|
||||
content = copy.copy(PGFA_DEVICE_COMMON_CONTENT)
|
||||
content.update(PGFA_DEVICES_SPECIAL_COMMON_CONTENT[dev])
|
||||
for k, v in content.items():
|
||||
p = os.path.join(path, k)
|
||||
if not v:
|
||||
os.mknod(p)
|
||||
elif type(v) is str:
|
||||
with open(p, 'a') as f:
|
||||
f.write(v + "\n")
|
||||
elif type(v) is list:
|
||||
with open(p, 'a') as f:
|
||||
f.writelines([l + "\n" for l in v])
|
||||
|
||||
|
||||
def gen_fpga_sub_dir(path):
|
||||
for d in PGFA_DEVICE_COMMON_SUB_DIR:
|
||||
p = os.path.join(path, d)
|
||||
os.makedirs(p)
|
||||
|
||||
|
||||
def gen_fpga_pf_soft_link(path, bdf):
|
||||
for k, v in PGFA_DEVICE_PF_SOFT_LINK.items():
|
||||
if callable(v):
|
||||
k, v = v(k, bdf)
|
||||
os.symlink(v, os.path.join(path, k))
|
||||
|
||||
|
||||
def gen_fpga_common_soft_link(path, bdf):
|
||||
for k, v in PGFA_DEVICE_COMMON_SOFT_LINK.items():
|
||||
os.symlink(v, os.path.join(path, k))
|
||||
|
||||
|
||||
def gen_fpga_vf_soft_link(path, bdf):
|
||||
for k, v in PGFA_DEVICE_VF_SOFT_LINK.items():
|
||||
if callable(v):
|
||||
k, v = v(k, bdf)
|
||||
os.symlink(v, os.path.join(path, k))
|
||||
|
||||
|
||||
def create_devices_path_and_files(tree, device_path, class_fpga_path,
|
||||
vf=False, pfinfo={}):
|
||||
for k, v in tree.items():
|
||||
bdf = v["bdf"]
|
||||
pci_path = "pci" + bdf.rsplit(":", 1)[0]
|
||||
bdf_path = os.path.join(device_path, pci_path, bdf)
|
||||
ln = "-".join([DEV_PREFIX, k])
|
||||
dev_path = os.path.join(bdf_path, "fpga", ln)
|
||||
os.makedirs(dev_path)
|
||||
gen_fpga_content(bdf_path, k)
|
||||
gen_fpga_sub_dir(bdf_path)
|
||||
if vf:
|
||||
gen_fpga_pf_soft_link(pfinfo["path"], bdf)
|
||||
gen_fpga_vf_soft_link(bdf_path, pfinfo["bdf"])
|
||||
pfinfo = {"path": bdf_path, "bdf": bdf}
|
||||
if "regions" in v:
|
||||
create_devices_path_and_files(
|
||||
v["regions"], device_path, class_fpga_path, True, pfinfo)
|
||||
source = dev_path.split("sys")[-1]
|
||||
os.symlink("../.." + source, os.path.join(class_fpga_path, ln))
|
||||
os.symlink("../../../" + bdf, os.path.join(dev_path, "device"))
|
||||
|
||||
|
||||
def create_devices_soft_link(class_fpga_path):
|
||||
devs = glob.glob1(class_fpga_path, "*")
|
||||
for dev in devs:
|
||||
path = os.path.realpath("%s/%s/device" % (class_fpga_path, dev))
|
||||
softlinks = copy.copy(PGFA_DEVICE_COMMON_SOFT_LINK)
|
||||
softlinks.update(
|
||||
PGFA_DEVICES_SPECIAL_SOFT_LINK[dev.rsplit("-", 1)[-1]])
|
||||
for k, v in softlinks.items():
|
||||
source = os.path.normpath(os.path.join(path, v))
|
||||
if not os.path.exists(source):
|
||||
os.makedirs(source)
|
||||
os.symlink(v, os.path.join(path, k))
|
||||
|
||||
|
||||
def create_fake_sysfs(prefix=""):
|
||||
sys_device = os.path.join(prefix, SYS_DEVICES)
|
||||
sys_class_fpga = os.path.join(prefix, SYS_CLASS_FPGA)
|
||||
basedir = os.path.dirname(sys_device)
|
||||
if os.path.exists(basedir):
|
||||
shutil.rmtree(basedir, ignore_errors=False, onerror=None)
|
||||
os.makedirs(sys_class_fpga)
|
||||
create_devices_path_and_files(FPGA_TREE, sys_device, sys_class_fpga)
|
||||
create_devices_soft_link(sys_class_fpga)
|
||||
|
||||
|
||||
def main():
|
||||
create_fake_sysfs()
|
||||
|
||||
|
||||
if __name__ == "__main__":
|
||||
parser = argparse.ArgumentParser(
|
||||
description="Generate a fake sysfs for intel FPGA.")
|
||||
group = parser.add_mutually_exclusive_group()
|
||||
group.add_argument("-v", "--verbose", action="store_true")
|
||||
group.add_argument("-q", "--quiet", action="store_true")
|
||||
parser.add_argument("-p", "--prefix", type=str,
|
||||
default="/tmp", dest="p",
|
||||
help='Set the prefix path of the fake sysfs. '
|
||||
'default "/tmp"')
|
||||
args = parser.parse_args()
|
||||
|
||||
create_fake_sysfs(args.p)
|
||||
Loading…
Reference in New Issue