155 lines
5.1 KiB
JSON
155 lines
5.1 KiB
JSON
{
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"namespace": "CIM::ProcessorAllocationSettingData",
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"display_name": "CIM Processor Allocation Setting",
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"description": "Properties related to the resource allocation settings of a processor (CPU) from Common Information Model (CIM) schema (http://www.dmtf.org/standards/cim). These are properties that identify processor setting data and may be specified to volume, image, host aggregate, flavor and Nova server as scheduler hint. For each property details, please refer to http://schemas.dmtf.org/wbem/cim-html/2/CIM_ProcessorAllocationSettingData.html.",
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"visibility": "public",
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"protected": true,
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"resource_type_associations": [
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{
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"name": "OS::Cinder::Volume",
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"prefix": "CIM_PASD_",
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"properties_target": "image"
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},
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{
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"name": "OS::Glance::Image",
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"prefix": "CIM_PASD_"
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},
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{
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"name": "OS::Nova::Aggregate",
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"prefix": "CIM_PASD_"
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},
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{
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"name": "OS::Nova::Flavor",
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"prefix": "CIM_PASD_"
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},
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{
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"name": "OS::Nova::Server",
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"properties_target": "scheduler_hint"
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}
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],
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"properties": {
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"InstructionSet": {
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"title": "Instruction Set",
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"description": "Identifies the instruction set of the processor within a processor architecture.",
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"operators": ["<or>"],
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"type": "string",
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"enum": [
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"x86:i386",
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"x86:i486",
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"x86:i586",
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"x86:i686",
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"x86:64",
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"IA-64:IA-64",
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"AS/400:TIMI",
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"Power:Power_2.03",
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"Power:Power_2.04",
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"Power:Power_2.05",
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"Power:Power_2.06",
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"S/390:ESA/390",
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"S/390:z/Architecture",
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"S/390:z/Architecture_2",
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"PA-RISC:PA-RISC_1.0",
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"PA-RISC:PA-RISC_2.0",
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"ARM:A32",
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"ARM:A64",
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"MIPS:MIPS_I",
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"MIPS:MIPS_II",
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"MIPS:MIPS_III",
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"MIPS:MIPS_IV",
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"MIPS:MIPS_V",
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"MIPS:MIPS32",
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"MIPS64:MIPS64",
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"Alpha:Alpha",
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"SPARC:SPARC_V7",
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"SPARC:SPARC_V8",
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"SPARC:SPARC_V9",
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"SPARC:SPARC_JPS1",
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"SPARC:UltraSPARC2005",
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"SPARC:UltraSPARC2007",
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"68k:68000",
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"68k:68010",
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"68k:68020",
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"68k:68030",
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"68k:68040",
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"68k:68060"
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]
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},
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"ProcessorArchitecture": {
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"title": "Processor Architecture",
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"description": "Identifies the processor architecture of the processor.",
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"operators": ["<or>"],
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"type": "string",
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"enum": [
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"x86",
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"IA-64",
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"AS/400",
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"Power",
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"S/390",
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"PA-RISC",
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"ARM",
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"MIPS",
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"Alpha",
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"SPARC",
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"68k"
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]
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},
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"InstructionSetExtensionName": {
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"title": "Instruction Set Extension",
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"description": "Identifies the instruction set extensions of the processor within a processor architecture.",
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"operators": ["<or>", "<all-in>"],
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"type": "array",
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"items": {
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"type": "string",
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"enum": [
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"x86:3DNow",
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"x86:3DNowExt",
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"x86:ABM",
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"x86:AES",
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"x86:AVX",
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"x86:AVX2",
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"x86:BMI",
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"x86:CX16",
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"x86:F16C",
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"x86:FSGSBASE",
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"x86:LWP",
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"x86:MMX",
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"x86:PCLMUL",
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"x86:RDRND",
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"x86:SSE2",
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"x86:SSE3",
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"x86:SSSE3",
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"x86:SSE4A",
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"x86:SSE41",
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"x86:SSE42",
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"x86:FMA3",
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"x86:FMA4",
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"x86:XOP",
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"x86:TBM",
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"x86:VT-d",
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"x86:VT-x",
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"x86:EPT",
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"x86:SVM",
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"PA-RISC:MAX",
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"PA-RISC:MAX2",
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"ARM:DSP",
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"ARM:Jazelle-DBX",
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"ARM:Thumb",
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"ARM:Thumb-2",
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"ARM:ThumbEE)",
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"ARM:VFP",
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"ARM:NEON",
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"ARM:TrustZone",
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"MIPS:MDMX",
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"MIPS:MIPS-3D",
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"Alpha:BWX",
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"Alpha:FIX",
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"Alpha:CIX",
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"Alpha:MVI"
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]
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}
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}
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},
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"objects": []
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}
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